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a
32-Channel, 14-Bit DAC with Precision Infinite Sample-and-Hold Mode AD5532B*
GENERAL DESCRIPTION
FEATURES High Integration: 32-Channel DAC in 12 mm 12 mm CSPBGA Guaranteed Monotonic to 14 Bits Infinite Sample-and-Hold Capability to 0.018% Accuracy Infinite Sample-and-Hold Total Unadjusted Error 2.5 mV Adjustable Voltage Output Range Readback Capability DSP/Microcontroller Compatible Serial Interface Output Impedance 0.5 Output Voltage Span 10 V Temperature Range -40 C to +85 C APPLICATIONS Automatic Test Equipment Optical Networks Level Setting Instrumentation Industrial Control Systems Data Acquisition Low Cost I/O
The AD5532B is a 32-channel, voltage output, 14-bit DAC with an additional precision infinite sample-and-hold mode. The selected DAC register is written to via the 3-wire serial interface and VOUT for this DAC is then updated to reflect the new contents of the DAC register. DAC selection is accomplished via address bits A0-A4. The output voltage range is determined by the offset voltage at the OFFS_IN pin and the gain of the output amplifier. It is restricted to a range from VSS + 2 V to VDD - 2 V because of the headroom of the output amplifier. The device is operated with AVCC = +5 V 5%, DVCC = +2.7 V to +5.25 V, VSS = -4.75 V to -16.5 V, and VDD = +8 V to +16.5 V and requires a stable 3 V reference on REF_IN as well as an offset voltage on OFFS_IN.
PRODUCT HIGHLIGHTS
1. 32-channel, 14-bit DAC in one package, guaranteed monotonic. 2. The AD5532B is available in a 74-lead CSPBGA with a body size of 12 mm 12 mm. 3. In infinite sample-and-hold mode, a total unadjusted error of 2.5 mV is achieved by laser-trimming on-chip resistors.
FUNCTIONAL BLOCK DIAGRAM
DVCC AVCC REF IN REF OUT OFFS IN VDD VSS
AD5532B
VOUT 0 VIN TRACK / RESET BUSY DAC GND AGND DAC DGND SER /PAR INTERFACE CONTROL LOGIC MODE MUX 14-BIT BUS DAC VOUT 31 ADC DAC
OFFS OUT
ADDRESS INPUT REGISTER
WR
SCLK DIN DOUT
SYNC / CS
A4-A0
CAL
OFFSET_SEL
*Protected by U.S. Patent No. 5,969,657; other patents pending.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
AD5532B-SPECIFICATIONS DV = +2.7 V to +5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFFS_IN = OV; Output Range from V + 2 V to V - 2 V. All outputs unloaded. All specifications T to T , unless otherwise noted.)
CC SS DD MIN MAX
(VDD = +8 V to +16.5 V, VSS = -4.75 V to -16.5 V; AVCC = +4.75 V to +5.25 V;
AD5532B-1 Parameter1
B Version2 14 0.39 1 90/170/250 3.52 -1/+0.5 0.006 0.018 2.5 12 1 10 3.51/3.52/3.53 0 to 3 70 40 1 20 1 0/4
Unit
Conditions/ Comments
DAC DC PERFORMANCE Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Offset Gain Full-Scale Error ISHA DC PERFORMANCE VIN to VOUT Nonlinearity3 Total Unadjusted Error (TUE) Offset Error Gain ISHA ANALOG INPUT (VIN) Input Voltage Range Input Lower Dead Band Input Upper Dead Band Input Current Input Capacitance4 ANALOG INPUT (OFFS_IN) Input Current Input Voltage Range VOLTAGE REFERENCE REF_IN Nominal Input Voltage Input Voltage Range4 Input Current REF_OUT Output Voltage Output Impedance4 Reference Temperature Coefficient4 ANALOG OUTPUTS (VOUT 0-31) Output Temperature Coefficient4, 5 DC Output Impedance4 Output Range Resistive Load4, 6 Capacitive Load4, 6 Short-Circuit Current4 DC Power-Supply Rejection Ratio4 DC Crosstalk4 ANALOG OUTPUT (OFFS_OUT) Output Temperature Coefficient4, 5 DC Output Impedance4 Output Range Output Current Capacitive Load
Bits % of FSR max LSB max mV min/typ/max typ % of FSR max % typ % max mV typ mV max mV typ mV max min/typ/max V mV max mV max A max pF typ A max V min/max
0.15% typ 0.5 LSB typ Monotonic See Figure 6.
After Offset and Gain Adjustment See TPC 6.
Nominal Input Range 50 mV typ. Referred to VIN. See Figure 7. 12 mV typ. Referred to VIN. See Figure 7. 100 nA typ. VIN acquired on one channel.
100 nA typ Output Range Restricted from VSS + 2 V to VDD - 2 V
3.0 2.85/3.15 1 3 280 60 10 0.5 VSS + 2/VDD - 2 5 100 7 -70 -70 250 10 1.3 50 to REF_IN - 12 10 100
V typ V min/max A max V typ k typ ppm/C typ ppm/C typ typ V min/max k min pF max mA typ dB dB V max ppm/C typ k typ mV typ A max pF max
<1 nA typ
100 A Output Load
VDD = +15 V 5% VSS = 15 V 5% Outputs Loaded
Source Current
-2-
REV. A
AD5532B
Parameter1 DIGITAL INPUTS Input Current Input Low Voltage
7
AD5532B-1 B Version2 10 0.8 0.4
Unit A max V max V max
V min V min mV typ pF max V max V min V max V min A max pF typ
Conditions/Comments 5 A typ DVCC = 5 V 5% DVCC = 3 V 10%
DVCC = 5 V 5% DVCC = 3 V 10%
Input High Voltage Input Hysteresis (SCLK and CS Only) Input Capacitance DIGITAL OUTPUTS (BUSY, DOUT)7 Output Low Voltage, DV CC = 5 V Output High Voltage, DVCC = 5 V Output Low Voltage, DVCC = 3 V Output High Voltage, DVCC = 3 V High Impedance Leakage Current High Impedance Output Capacitance POWER REQUIREMENTS Power Supply Voltages VDD VSS AVCC DVCC Power Supply Currents8 IDD ISS AICC DICC Power Dissipation8
NOTES
1 2
2.4 2.0 200 10 0.4 4.0 0.4 2.4 1 15
Sinking 200 A Sourcing 200 A Sinking 200 A Sourcing 200 A DOUT Only DOUT Only
8/16.5 -4.75/-16.5 4.75/5.25 2.7/5.25 15 15 33 1.5 280
V min/max V min/max V min/max V min/max mA max mA max mA max mA max mW typ 10 mA typ. All channels full-scale. 10 mA typ. All channels full-scale. 26 mA typ 1 mA typ VDD = +10 V, VSS = -5 V
See Terminology section. B Version: Industrial temperature range -40C to +85C; typical at +25C. 3 Input range 100 mV to 2.96 V. 4 Guaranteed by design and characterization, not production tested. 5 AD780 as reference for the AD5532B. 6 Ensure that you do not exceed T J (max). See Absolute Maximum Ratings section.
7
8
Guaranteed by design and characterization, not production tested.
Output unloaded. Specifications subject to change without notice.
REV. A
-3-
AD5532B AC CHARACTERISTICS
Parameter1
(VDD = +8 V to +16.5 V, VSS = -4.75 V to -16.5 V; AVCC = +4.75 V to +5.25 V; DVCC = +2.7 V to +5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFF_IN = OV; All specifications TMIN to TMAX, unless otherwise noted.)
AD5532B-1 B Version2
3
Unit s max s max nV-s typ nV-s typ nV-s typ nV-s typ nV/Hz typ s max s max nV-s typ
Conditions/Comments 500 pF, 5 k Load Full-Scale Change 500 pF, 5 k Load; 0 V to 3 V Step 1 LSB Change Around Major Carry
DAC AC CHARACTERISTICS Output Voltage Settling Time OFFS_IN Settling Time Digital-to-Analog Glitch Impulse Digital Crosstalk Analog Crosstalk Digital Feedthrough Output Noise Spectral Density @ 1 kHz ISHA AC CHARACTERISTICS Output Voltage Settling Time3 Acquisition Time AC Crosstalk3
NOTES 1 See Terminology section.
2 3
22 10 1 5 1 0.2 400 3 16 5
Outputs Unloaded
B Version: Industrial temperature range -40C to +85C; typical at +25C. Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Parameter1, 2 t1 t2 t3 t4 t5 t6
Limit at TMIN, TMAX (B Version) 0 0 50 50 20 7
Unit ns min ns min ns min ns min ns min ns min
Conditions/Comments CS to WR Setup Time CS to WR Hold Time CS Pulsewidth Low WR Pulsewidth Low A4-A0, CAL, OFFS_SEL to WR Setup Time A4-A0, CAL, OFFS_SEL to WR Hold Time
NOTES 1 See Parallel Interface Timing Diagram. 2 Guaranteed by design and characterization, not production tested. Specifications subject to change without notice.
SERIAL INTERFACE
Parameter1, 2 fCLKIN t1 t2 t3 t4 t5 t6 t7 t8 4 t9 4 t10 t11 t125
3
Limit at TMIN, TMAX (B Version) 14 28 28 15 50 15 5 5 20 60 400 400 7
Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns max ns max ns min ns min ns min
Conditions/Comments SCLK Frequency SCLK High Pulsewidth SCLK Low Pulsewidth SYNC Falling Edge to SCLK Falling Edge Setup Time SYNC Low Time DIN Setup Time DIN Hold Time SYNC Falling Edge to SCLK Rising Edge Setup Time for Readback SCLK Rising Edge to DOUT Valid SCLK Falling Edge to DOUT High Impedance 10th SCLK Falling Edge to SYNC Falling Edge for Readback 24th SCLK Falling Edge to SYNC Falling Edge for DAC Mode Write SCLK Falling Edge to SYNC Falling Edge for Readback
NOTES 1 See Serial Interface Timing Diagrams. 2 Guaranteed by design and characterization, not production tested. 3 In ISHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns. 4 These numbers are measured with the load circuit of Figure 2. 5 SYNC should be taken low while SCLK is low for readback. Specifications subject to change without notice.
-4-
REV. A
AD5532B
PARALLEL INTERFACE TIMING DIAGRAM
CS
200 A IOL
WR
TO OUTPUT PIN
1.6V CL 50pF 200 A IOH
A4-A0, CAL, OFFS SEL
Figure 1. Parallel Write (ISHA Mode Only)
Figure 2. Load Circuit for DOUT Timing Specifications
SERIAL INTERFACE TIMING DIAGRAMS
t1
SCLK 1 2 3 4 5 6 7 8 9 10
t3
SYNC
t2
t4
t5 t6
DIN MSB LSB
Figure 3. 10-Bit Write (ISHA Mode and Both Readback Modes)
t1
SCLK 1 2 3 4 5 21 22 23 24 1
t3
SYNC
t2
t4
t5 t6
t 11
DIN MSB LSB
Figure 4. 24-Bit Write (DAC Mode)
t7
SCLK
t1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
10
t12
SYNC
t2
t10
DOUT MSB
t4
t8
t9
LSB
Figure 5. 14-Bit Read (Both Readback Modes)
REV. A
-5-
AD5532B
ABSOLUTE MAXIMUM RATINGS 1, 2
(TA = 25C, unless otherwise noted.)
Max Continuous Load Current at TJ = 70C, per Channel Group . . . . . . . . . . . . . . . . . . . . . . . 15.5 mA4
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. 3 This limit includes load power. 4 This maximum allowed continuous load current is spread over eight channels, with channels grouped as follows: Group 1: Channels 3, 4, 5, 6, 7, 8, 9, 10 Group 2: Channels 14, 16, 18, 20, 21, 24, 25, 26 Group 3: Channels 15, 17, 19, 22, 23, 27, 28, 29 Group 4: Channels 0, 1, 2, 11, 12, 13, 30, 31 For higher junction temperatures, derate as follows: Max Continuous Load Current per Group (mA) 1.55 9.025 6.925 5.175 3.425 2.55 1.5
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +17 V VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to -17 V AVCC to AGND, DAC_GND . . . . . . . . . . . . . -0.3 V to +7 V DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Digital Inputs to DGND . . . . . . . . . . -0.3 V to DVCC + 0.3 V Digital Outputs to DGND . . . . . . . . . -0.3 V to DVCC + 0.3 V REF_IN to AGND, DAC_GND . . . . -0.3 V to AVCC + 0.3 V VIN to AGND, DAC_GND . . . . . . . . -0.3 V to AVCC + 0.3 V VOUT0-31 to AGND . . . . . . . . . . VSS - 0.3 V to VDD + 0.3 V OFFS_IN to AGND . . . . . . . . . . VSS - 0.3 V to VDD + 0.3 V OFFS_OUT to AGND . . . . AGND - 0.3 V to AVCC + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Operating Temperature Range Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . 150C 74-Lead CSPBGA Package, JA Thermal Impedance . . 41C/W Reflow Soldering Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220C Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec Max Power Dissipation . . . . . . . . . . . . (150C - TA)/JA mW3
TJ (C) 70 90 100 110 125 135 150
ORDERING GUIDE
Model AD5532BBC-1 AD5532ABC-1* AD5532ABC-2* AD5532ABC-3* AD5532ABC-5* AD5533ABC-1* AD5533BBC-1* EVAL-AD5532EB
*Separate Data Sheet.
Function 32 DACs, 32-Channel Precision ISHA 32 DACs, 32-Channel ISHA 32 DACs, 32-Channel ISHA 32 DACs, 32-Channel ISHA 32 DACs, 32-Channel ISHA 32-Channel ISHA Only 32-Channel Precision ISHA Only Evaluation Board
Output Impedance (Typ) 0.5 0.5 0.5 500 1 k 0.5 0.5
Output Voltage Span (V) 10 10 20 10 10 10 10
Package Description 74-Lead CSPBGA 74-Lead CSPBGA 74-Lead CSPBGA 74-Lead CSPBGA 74-Lead CSPBGA 74-Lead CSPBGA 74-Lead CSPBGA
Package Option BC-74 BC-74 BC-74 BC-74 BC-74 BC-74 BC-74
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5532B features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-6-
REV. A
AD5532B
PIN CONFIGURATION
1 A B C D E F G H J K L 1 2 3 4 5 6 7 8 9 10 11 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L
74-Lead CSPBGA Ball Configuration
CSPBGA Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C6
Ball Name NC* A4 A2 A0 CS/SYNC DVCC SCLK OFFSET_SEL BUSY TRACK/RESET NC* VO16 NC* A3 A1 WR DGND DIN CAL SER/PAR DOUT REF_IN VO18 DAC_GND1 NC*
CSPBGA Number C10 C11 D1 D2 D10 D11 E1 E2 E10 E11 F1 F2 F10 F11 G1 G2 G10 G11 H1 H2 H10 H11 J1 J2 J6
Ball Name AVCC1 REF_OUT VO20 DAC_GND2 AVCC2 OFFS_OUT VO26 VO14 AGND1 OFFS_IN VO25 VO21 AGND2 VO6 VO24 VO8 VO5 VO3 VO23 VIN VO4 VO7 VO22 VO19 VSS2
CSPBGA Number J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11
Ball Name VO9 VO11 VO17 VO15 VO27 VSS3 VSS1 VSS4 VDD2 VO2 VO10 VO13 VO12 NC* VO28 VO29 VO30 VDD3 VDD1 VDD4 VO31 VO0 VO1 NC*
*NC = Not Connected
REV. A
-7-
AD5532B
PIN FUNCTION DESCRIPTIONS
Mnemonic AGND (1-2) AVCC (1-2) VDD (1-4) VSS (1-4) DGND DVCC DAC_GND (1-2) REF_IN REF_OUT VOUT (0-31) VIN A4-A11, A02 CAL1 CS/SYNC WR1 OFFSET_SEL1 SCLK2 DIN2 DOUT SER/PAR1 OFFS_IN OFFS_OUT BUSY TRACK/RESET2
Description Analog GND Pins Analog Supply Pins. Voltage range from 4.75 V to 5.25 V. VDD Supply Pins. Voltage range from 8 V to 16.5 V. VSS Supply Pins. Voltage range from -4.75 V to -16.5 V. Digital GND Pins Digital Supply Pins. Voltage range from 2.7 V to 5.25 V. Reference GND Supply for all the DACs Reference Voltage for Channels 0-31 Reference Output Voltage Analog Output Voltages from the 32 Channels Analog Input Voltage. Connect this to AGND if operating in DAC mode only. Parallel Interface. 5-address pins for 32 channels. A4 = MSB of channel address. A0 = LSB. Parallel Interface. Control input that allows all 32 channels to acquire VIN simultaneously. This pin is both the active low chip select pin for the parallel interface and the frame synchronization pin for the serial interface. Parallel Interface. Write pin. Active low. This is used in conjunction with the CS pin to address the device using the parallel interface. Parallel Interface. Offset select pin. Active high. This is used to select the offset channel. Serial Clock Input for Serial Interface. This operates at clock speeds up to 14 MHz (20 MHz in ISHA mode). Data Input for Serial Interface. Data must be valid on the falling edge of SCLK. Output from the DAC Registers for Readback. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. This pin allows the user to select whether the serial or parallel interface will be used. If the pin is tied low, the parallel interface will be used. If it is tied high, the serial interface will be used. Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to this pin if the user wants to drive this pin with the offset channel. Offset Output. This is the acquired/programmed offset voltage that can be tied to OFFS_IN to offset the span. This output tells the user when the input voltage is being acquired. It goes low during acquisition and returns high when the acquisition operation is complete. If this input is held high, VIN is acquired once the channel is addressed. While it is held low, the input to the gain/offset stage is switched directly to VIN. The addressed channel begins to acquire VIN on the rising edge of TRACK. See TRACK Input section for further information. This input can also be used as a means of resetting the complete device to its power-on-reset conditions. This is achieved by applying a low going pulse of between 90 ns and 200 ns to this pin. See section on RESET Function for further details.
NOTES 1 Internal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition. 2 Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition.
OUTPUT VOLTAGE FULL-SCALE ERROR RANGE IDEAL GAIN IDEAL TRANSFER FUNCTION OFFSET RANGE 0 DAC CODE REFIN
VOUT GAIN ERROR + OFFSET ERROR
IDEAL TRANSFER FUNCTION
OFFSET ERROR
ACTUAL TRANSFER FUNCTION
IDEAL GAIN
50mV 16k
0V
70mV
2.96 3V UPPER DEAD BAND
VIN
LOWER DEAD BAND
Figure 6. DAC Transfer Function (OFFS_IN = 0)
Figure 7. ISHA Transfer Function
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REV. A
AD5532B
TERMINOLOGY DAC MODE Integral Nonlinearity (INL) Output Noise Spectral Density
This is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is expressed as a percentage of full-scale span.
Differential Nonlinearity (DNL)
This is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per root Hertz). It is measured by loading all DACs to midscale and measuring noise at the output. It is measured in nV/Hz.
Output Temperature Coefficient
Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of 1 LSB maximum ensures monotonicity.
Offset
This is a measure of the change in analog output with changes in temperature. It is expressed in ppm/C.
DC Power Supply Rejection Ratio
DC power supply rejection ratio (PSRR) is a measure of the change in analog output for a change in supply voltage (VDD and VSS). It is expressed in dBs. VDD and VSS are varied 5%.
DC Crosstalk
Offset is a measure of the output with all zeros loaded to the DAC and OFFS_IN = 0. Since each DAC is lifted off the ground by approximately 50 mV, this output will typically be:
VOUT = GAIN x 50 mV
Full-Scale Error
This is the change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of all other DACs. It is expressed in V.
ISHA MODE Total Unadjusted Error (TUE)
This is a measure of the output error with all 1s loaded to the DAC. It is expressed as a percentage of full-scale range. It includes the offset error. See Figure 6. It is calculated as: Full-Scale Error = VOUT ( Full Scale ) - ( Ideal Gain x REFIN ) where Ideal Gain = 3.52 for AD5532B - 1
Output Settling Time
This is a comprehensive specification that includes relative accuracy, gain and offset errors. It is measured by sampling a range of voltages on VIN and comparing the measured voltages on VOUT to the ideal value. It is expressed in mV.
VIN to VOUT Nonlinearity
This is a measure of the maximum deviation from a straight line passing through the endpoints of the VIN versus VOUT transfer function. It is expressed as a percentage of the full-scale span.
Offset Error
This is the time taken from when the last data bit is clocked into the DAC until the output has settled to within 0.39%.
OFFS_IN Settling Time
This is the time taken from a 0 V-3 V step change in input voltage on OFFS_IN until the output has settled to within 0.39%.
Digital-to-Analog Glitch Impulse
This is a measure of the output error when VIN = 70 mV. Ideally, with VIN = 70 mV:
VOUT = (Gain x 70) - (Gain - 1) x VOFFS _ IN mV
Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal). It is expressed in mV and can be positive or negative. See Figure 7.
Gain Error
[
]
This is the area of the glitch injected into the analog output when the code in the DAC register changes state. It is specified as the area of the glitch in nV-secs when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11).
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC at midscale while a full-scale code change (all 1s to all 0s and vice versa) is being written to another DAC. It is expressed in nV-secs.
Analog Crosstalk
This is a measure of the span error of the analog channel. It is the deviation in slope of the transfer function expressed in mV. See Figure 7. It is calculated as: Gain Error = Actual Full-Scale Output - Ideal Full-Scale Output - Offset Error where Ideal Full-Scale Output = (Gain 2.96) - [(Gain - 1) VOFFS_IN] AC Crosstalk This is the area of the glitch that occurs on the output of one channel while another channel is acquiring. It is expressed in nV-secs.
Output Settling Time
This the area of the glitch transferred to the output (VOUT) of one DAC due to a full-scale change in the output (VOUT) of another DAC. The area of the glitch is expressed in nV-secs.
Digital Feedthrough
This is a measure of the impulse injected into the analog outputs from the digital control inputs when the part is not being written to, i.e., CS/SYNC is high. It is specified in nV-secs and is measured with a worst-case change on the digital input pins, e.g., from all 0s to all 1s and vice versa.
This is the time taken from when BUSY goes high to when the output has settled to 0.018%.
Acquisition Time
This is the time taken for the VIN input to be acquired. It is the length of time that BUSY stays low.
REV. A
-9-
AD5532B -Typical Performance Characteristics
1.0 0.8 0.6 DNL ERROR - LSBs 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0
0 10
VREFIN = 3V VOFFS_IN = 0V TA = 25 C
5.370
40
5.360
DAC LOADED TO MIDSCALE VREFIN = 3V VOFFS_IN = 0V
FREQUENCY
20
VOUT - V
0 0.05 0.10 FSR - % 0.15
30
5.350
5.340
5.330
0
2k
4k
6k 8k 10k 12k 14k 16k DAC CODE
5.320 -40
0 40 TEMPERATURE - C
80
TPC 1. Typical DNL Plot
TPC 2. INL Error Distribution at 25C (DAC Mode)
TPC 3. VOUT vs. Temperature
3.530 TA = 25 C VREFIN = 3V VIN = 1V 3.525
VOUT - V
10.0
TA = 25 C VREFIN = 3V 8.0 VOFFS_IN = 0.5V 6.0
40
FREQUENCY
VOUT - V
4.0
20
3.520
2.0
0.0
3.515
6
4 2 0 -2 -4 SINK/SOURCE CURRENT - mA
-6
-2.0 TIME BASE - 2 s/DIV
0 -4 -3 -2 -1 0 1 2 3 4 5 6 7 TOTAL UNADJUSTED ERROR mV
8
TPC 4. VOUT Source and Sink Capability
TPC 5. Full-Scale Settling Time
TPC 6. TUE Distribution at 25C (ISHA Mode)
0.024 0.020 0.016 0.012
TA = 25 C VREFIN = 3V VOFFS_IN = 0V
100 90
70k 63791 60k 50k TA = 25 C VREFIN = 3V VIN = 1.5V VOFFS_IN = 0V
5V BUSY VOUT TA = 25 C VREFIN = 3V VIN = 0 1.5V
VOUT ERROR - %
0.004 0.000 -0.004 -0.008 -0.012 -0.016 -0.020 -0.024 0.1 2.96
1V 2s
10 0%
FREQUENCY
0.008
40k 30k 20k 10k 0 200 5.2670 5.2676 VOUT - V 1545 5.2682
VIN - V
TPC 7. VIN to VOUT Accuracy After Offset and Gain Adjustment (ISHA Mode)
TPC 8. Acquisition Time and Output Settling Time (ISHA Mode)
TPC 9. ISHA Mode Repeatability (64 K Acquisitions)
-10-
REV. A
AD5532B
FUNCTIONAL DESCRIPTION ISHA Mode
The AD5532B can be thought of as consisting of 32 DACs and an ADC (for ISHA mode) in a single package. In DAC mode, a 14-bit digital word is loaded into one of the 32 DAC registers via the serial interface. This is then converted (with gain and offset) into an analog output voltage (VOUT0-VOUT31). To update a DAC's output voltage, the required DAC is addressed via the serial port. When the DAC address and code have been loaded, the selected DAC converts the code. On power-on, all the DACs, including the offset channel, are loaded with zeros. Each of the 33 DACs is offset internally by 50 mV (typ) from GND so the outputs VOUT0 to VOUT31 are 50 mV (typ) on power-on if the OFFS_IN pin is driven directly by the on-board offset channel (OFFS_OUT), i.e., if OFFS_IN = OFFS_OUT = 50 mV = > VOUT = (Gain x VDAC) - (Gain -1) x VOFFS_IN = 50 mV.
Output Buffer Stage--Gain and Offset
In ISHA mode the input voltage VIN is sampled and converted into a digital word. The noninverting input to the output buffer (gain and offset stage) is tied to VIN during the acquisition period to avoid spurious outputs while the DAC acquires the correct code. This is completed in 16 s max. At this time, the updated DAC output assumes control of the output voltage. The output voltage of the DAC is connected to the noninverting input of the output buffer. Since the channel output voltage is effectively the output of a DAC, there is no droop associated with it. As long as power is maintained to the device, the output voltage will remain constant until this channel is addressed again. Since the internal DACs are offset by 70 mV (max) from GND, the minimum VIN in ISHA mode is 70 mV. The maximum VIN is 2.96 V due to the upper dead band of 40 mV (max).
Analog Input (ISHA Mode)
The function of the output buffer stage is to translate the 50 mV-3 V typical output of the DAC to a wider range. This is done by gaining up the DAC output by 3.52 and offsetting the voltage by the voltage on OFFS_IN pin.
VOUT = 3.52 x VDAC - 2.52 x VOFFS _ IN
VDAC is the output of the DAC. VOFFS_IN is the voltage at the OFFS_IN pin. Table I shows how the output range on VOUT relates to the offset voltage supplied by the user:
Table I. Sample Output Voltage Ranges
The equivalent analog input circuit is shown in Figure 8. The capacitor C1 is typically 20 pF and can be attributed to pin capacitance and 32 off-channels. When a channel is selected, an extra 7.5 pF (typ) is switched in. This capacitor C2 is charged to the previously acquired voltage on that particular channel so it must charge/discharge to the new level. It is essential that the external source can charge/discharge this additional capacitance within 1 s to 2 s of channel selection so that VIN can be acquired accurately. For this reason a low impedance source is recommended.
ADDRESSED CHANNEL VIN C1 20pF C2 7.5pF
VOFFS_IN (V) 0 1 2.130
VDAC (Typ) (V) 0.05 to 3 0.05 to 3 0.05 to 3
VOUT (Typ) (V) 0.176 to 10.56 -2.34 to +8.04 -5.192 to +5.192
Figure 8. Analog Input Circuit
VOUT is limited only by the headroom of the output amplifiers. VOUT must be within maximum ratings.
Offset Voltage Channel
Large source impedances will significantly affect the performance of the ADC. This may necessitate the use of an input buffer amplifier.
TRACK Function (ISHA Mode)
The offset voltage can be externally supplied by the user at OFFS_IN or it can be supplied by an additional offset voltage channel on the device itself. The offset can be set up in two ways. In ISHA mode the required offset voltage is set up on VIN and acquired by the offset channel. In DAC mode, the code corresponding to the offset value is loaded directly into the offset DAC. This offset channel's DAC output is directly connected to the OFFS_OUT pin. By connecting OFFS_OUT to OFFS_IN this offset voltage can be used as the offset voltage for the 32 output amplifiers. The offset must be chosen so that VOUT is within maximum ratings.
Reset Function
Normally in ISHA mode of operation, TRACK is held high and the channel begins to acquire when it is addressed. However, if TRACK is low when the channel is addressed, VIN is switched to the output buffer and an acquisition on the channel will not occur until a rising edge of TRACK. At this stage the BUSY pin will go low until the acquisition is complete, at which point the DAC assumes control of the voltage to the output buffer and VIN is free to change again without affecting this output value. This is useful in an application where the user wants to ramp up VIN until VOUT reaches a particular level (Figure 9). VIN does not need to be acquired continuously while it is ramping up. TRACK can be kept low and only when VOUT has reached its desired voltage is TRACK brought high. At this stage, the acquisition of VIN begins. In the example shown, a desired voltage is required on the output of the pin driver. This voltage is represented by one input to a comparator. The microcontroller/microprocessor ramps up the input voltage on VIN through a DAC. TRACK is kept low while the voltage on VIN ramps up so that VIN is not continually acquired. When the desired voltage is reached on the output
The reset function on the AD5532B can be used to reset all nodes on this device to their power-on-reset condition. This is implemented by applying a low going pulse of between 90 ns and 200 ns to the TRACK/RESET pin on the device. If the applied pulse is less than 90 ns, it is assumed to be a glitch and no operation takes place. If the applied pulse is wider than 200 ns, this pin adopts its track function on the selected channel, VIN is switched to the output buffer, and an acquisition on the channel will not occur until a rising edge of TRACK. REV. A
-11-
AD5532B
PIN DRIVER VIN BUSY TRACK OUTPUT STAGE VOUT1 DEVICE UNDER TEST
CONTROLLER
DAC
ACQUISITION CIRCUIT
AD5532B
THRESHOLD VOLTAGE ONLY ONE CHANNEL SHOWN FOR SIMPLICITY
Figure 9. Typical ATE Circuit Using TRACK Input
of the pin driver, the comparator output switches. The C/P then knows what code is required to be input in order to obtain the desired voltage at the DUT. The TRACK input is now brought high and the part begins to acquire VIN. At this stage, BUSY goes low until VIN has been acquired. The output buffer is then switched from VIN to the output of the DAC.
MODES OF OPERATION
Table II. Modes of Operation
Mode Bit 1 0 0 1 1
1. ISHA Mode
Mode Bit 2 0 1 0 1
Operating Mode ISHA Mode DAC Mode Acquire and Readback Readback
The AD5532B can be used in four different modes of operation. These modes are set by two mode bits, the first two bits in the serial word.
In this mode, a channel is addressed and that channel acquires the voltage on VIN. This mode requires a 10-bit write (see Figure 3) to address the relevant channel (VOUT0- VOUT31, offset channel or all channels). MSB is written first.
LSB
MSB 0 0 CAL OFFSET SEL 0 TEST BIT
A4 -A0
MODE BIT 1 MODE BIT 2 MODE BITS
a. 10-Bit Input Serial Write Word (ISHA Mode)
MSB 0 1 CAL OFFSET SEL 0 TEST BIT MODE BITS A4 -A0 LSB DB13-DB0
b. 24-Bit Input Serial Write Word (DAC Mode)
MSB 1 0 CAL OFFSET SEL 0 TEST BIT MODE BITS 10-BIT SERIAL WORD WRITTEN TO PART 14-BIT DATA READ FROM PART AFTER NEXT FALLING EDGE OF SYNC (DB13 = MSB OF DAC WORD) LSB A4 -A0 MSB DB1 3 -DB0 LSB
c. Input Serial Interface (Acquire and Readback Mode)
MSB 1 1 CAL OFFSET SEL 0 TEST BIT MODE BITS 10-BIT SERIAL WORD WRITTEN TO PART 14-BIT DATA READ FROM PART AFTER NEXT FALLING EDGE OF SYNC (DB13 = MSB OF DAC WORD) A4 -A0 LSB MSB DB1 3 -DB0 LSB
d. Input Serial Interface (Readback Mode) Figure 10. Serial Interface Formats
-12-
REV. A
AD5532B
2. DAC Mode Test Bit
In this standard mode, a selected DAC register is loaded serially. This requires a 24-bit write (10 bits to address the relevant DAC plus an extra 14 bits of DAC data). (See Figure 4.) MSB is written first. The user must allow 400 ns (min) between successive writes in DAC mode.
3. Acquire and Readback Mode
This must be set low for correct operation of the part.
A4-A0 Bits
Used to address any one of the 32 channels (A4 = MSB of address, A0 = LSB).
DB13-DB0 Bits
This mode allows the user to acquire VIN and read back the data in a particular DAC register. The relevant channel is addressed (10-bit write, MSB first) and VIN is acquired in 16 s (max). Following the acquisition, after the next falling edge of SYNC, the data in the relevant DAC register is clocked out onto the DOUT line in a 14-bit serial format. (See Figure 5.) The full acquisition time must elapse before the DAC register data can be clocked out.
4. Readback Mode
These are used to write a 14-bit word into the addressed DAC register. Clearly, this is only valid when in DAC mode. The serial interface is designed to allow easy interfacing to most microcontrollers and DSPs, e.g., PIC16C, PIC17C, QSPITM, SPITM, DSP56000, TMS320, and ADSP-21xx, without the need for any glue logic. When interfacing to the 8051, the SCLK must be inverted. The Microprocessor/Microcontroller Interface section explains how to interface to some popular DSPs and microcontrollers. Figures 3, 4, and 5 show the timing diagram for a serial read and write to the AD5532B. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial shift registers. Any further edges on SYNC are ignored until the correct number of bits are shifted in or out. Once the correct number of bits for the selected mode have been shifted in or out, the SCLK is ignored. In order for another serial transfer to take place, the counter must be reset by the falling edge of SYNC. In readback, the first rising SCLK edge after the falling edge of SYNC causes DOUT to leave its high impedance state and data is clocked out onto the DOUT line and also on subsequent SCLK rising edges. The DOUT pin goes back into a high impedance state on the falling edge of the fourteenth SCLK. Data on the DIN line is latched in on the first SCLK falling edge after the falling edge of the SYNC signal and on subsequent SCLK falling edges. During readback DIN is ignored. The serial interface will not shift data in or out until it receives the falling edge of the SYNC signal.
PARALLEL INTERFACE (ISHA Mode Only)
Again, this is a readback mode but no acquisition is performed. The relevant channel is addressed (10-bit write, MSB first) and on the next falling edge of SYNC, the data in the relevant DAC register is clocked out onto the DOUT line in a 14-bit serial format. (See Figure 5.) The user must allow 400 ns (min) between the last SCLK falling edge in the 10-bit write and the falling edge of SYNC in the 14-bit readback. The serial write and read words can be seen in Figure 10. This feature allows the user to read back the DAC register code of any of the channels. In DAC mode, this is useful in verification of write cycles. In ISHA mode, readback is useful if the system has been calibrated and the user wants to know what code in the DAC corresponds to a desired voltage on VOUT. If the user requires this voltage again, the user can input the code directly to the DAC register without going through the acquisition sequence.
INTERFACES SERIAL INTERFACE
The SER/PAR pin is tied high to enable the serial interface and to disable the parallel interface. The serial interface is controlled by four pins as follows:
SYNC, DIN, SCLK
The SER/PAR bit must be tied low to enable the parallel interface and disable the serial interface. The parallel interface is controlled by nine pins.
CS
Standard 3-wire interface pins. The SYNC pin is shared with the CS function of the parallel interface.
DOUT
Active low package select pin. This pin is shared with the SYNC function for the serial interface.
WR
Data out pin for reading back the contents of the DAC registers. The data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
Mode Bits
Active low write pin. The values on the address pins are latched on a rising edge of WR.
A4-A0
There are four different modes of operation as described above.
Cal Bit
Five address pins (A4 = MSB of address, A0 = LSB). These are used to address the relevant channel (out of a possible 32).
Offset_Sel
In DAC mode, this is a test bit. When it is high it is used to load all zeros or all ones to the 32 DACs simultaneously. In ISHA mode, all 32 channels acquire VIN simultaneously when this bit is high. In ISHA mode, the acquisition time is then 45 s (typ) and accuracy may be reduced. This bit is set low for normal operation.
Offset_Sel Bit
Offset select pin. This has the same function as the Offset_Sel bit in the serial interface. When it is high, the offset channel is addressed. The address on A4-A0 is ignored in this case.
Cal
If this is set high, the offset channel is selected and Bits A4-A0 are ignored.
*SPI and QSPI are trademarks of Motorola, Inc.
When this pin is high, all 32 channels acquire VIN simultaneously. The acquisition time is then 45 s (typ) and accuracy may be reduced.
REV. A
-13-
AD5532B
MICROPROCESSOR INTERFACING AD5532B to ADSP-21xx Interface
The ADSP-21xx family of DSPs is easily interfaced to the AD5532B without the need for extra logic. A data transfer is initiated by writing a word to the TX register after the SPORT has been enabled. In a write sequence, data is clocked out on each rising edge of the DSP's serial clock and clocked into the AD5532B on the falling edge of its SCLK. In readback, 16 bits of data are clocked out of the AD5532B on each rising edge of SCLK and clocked into the DSP on the rising edge of SCLK. DIN is ignored. The valid 14 bits of data will be centered in the 16-bit RX register when using this configuration. The SPORT control register should be set up as follows: TFSW INVRFS DTYPE ISCLK TFSR IRFS ITFS SLEN SLEN SLEN = = = = = = = = = = RFSW = 1, Alternate Framing INVTFS = 1, Active Low Frame Signal 00, Right Justify Data 1, Internal Serial Clock RFSR = 1, Frame Every Word 0, External Framing Signal 1, Internal Framing Signal 1001, 10-Bit Data-Words (ISHA Mode Write) 0111, 3 8-Bit Data-Words (DAC Mode Write) 1111, 16-Bit Data-Words (Readback Mode)
When data is being transmitted to the AD5532B, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to transmit 10 data bits in ISHA mode, it is important to left-justify the data in the SPDR register. PC7 must be pulled low to start a transfer. It is taken high and pulled low again before any further read/write cycles can take place.
AD5532B to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit = 0. This is done by writing to the synchronous serial port control register (SSPCON). See PIC16/17 Microcontroller User Manual. In this example, I/O port RA1 is being used to pulse SYNC and enable the serial port of the AD5532B. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, two or three consecutive read/write operations are needed depending on the mode. Figure 13 shows the connection diagram.
AD5532B*
SCLK DOUT DIN SYNC
PIC16C6x/7x*
SCK/RC3 SDO/RC5 SDI/RC4 RA1
Figure 11 shows the connection diagram.
AD5532B*
DOUT SYNC
ADSP-2101/
DR ADSP-2103* TFS RFS DIN DT SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. AD5532B to PIC16C6x/7x Interface
AD5532B to 8051
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. AD5532B to ADSP-2101/ADSP-2103 Interface
AD5532B to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1), clock polarity bit (CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR)--see 68HC11 User Manual. SCK of the 68HC11 drives the SCLK of the AD5532B, the MOSI output drives the serial data line (DIN) of the AD5532B, and the MISO input is driven from DOUT. The SYNC signal is derived from a port line (PC7). A connection diagram is shown in Figure 12.
AD5532B*
DOUT SYNC SCLK DIN PC7 SCK MOSI
The AD5532B requires a clock synchronized to the serial data. The 8051 serial interface must therefore be operated in Mode 0. In this mode, serial data enters and exits through RxD and a shift clock is output on TxD. Figure 14 shows how the 8051 is connected to the AD5532B. Because the AD5532B shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. The AD5532B requires its data with the MSB first. Since the 8051 outputs the LSB first, the transmit routine must take this into account.
AD5532B*
SCLK DOUT DIN SYNC P1.1 TxD RxD
8051*
*ADDITIONAL PINS OMITTED FOR CLARITY
MC68HC11*
MISO
Figure 14. AD5532B to 8051 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 12. AD5532B to MC68HC11 Interface
-14-
REV. A
AD5532B
APPLICATION CIRCUITS AD5532B in a Typical ATE System Typical Application Circuit (ISHA Mode)
The AD5532B is ideally suited for use in automatic test equipment. Several DACs are required to control pin drivers, comparators, active loads, and signal timing. Traditionally, sample-and-hold devices were used in these applications. The AD5532B has several advantages: no refreshing is required, there is no droop, pedestal error is eliminated, and there is no need for extra filtering to remove glitches. Overall a higher level of integration is achieved in a smaller area (see Figure 15).
PARAMETRIC MEASUREMENT SYSTEM BUS UNIT DAC DAC DAC ACTIVE LOAD
The AD5532B can be used to set up voltage levels on 32 channels as shown in the circuit below. An AD780 provides the 3 V reference for the AD5532B, and for the AD5541 16-bit DAC. A simple 3-wire serial interface is used to write to the AD5541. Because the AD5541 has an output resistance of 6.25 kW (typ), the time taken to charge/discharge the capacitance at the VIN pin is significant. Thus an AD820 is used to buffer the DAC output. Note that it is important to minimize noise on VIN and REFIN when laying out this circuit.
AVCC AVCC DVCC VSS
VDD
CS DIN SCLK DRIVER DAC
AD5541*
AD820
VIN
AD5532B*
OFFS_IN OFFS_OUT REFIN
VOUT 0-31
STORED DATA AND INHIBIT PATTERN FORMATTER
REF
DAC PERIOD GENERATION AND DELAY TIMING
DUT
AD780*
VOUT
DAC COMPARE REGISTER DAC COMPARATOR
SCLK DIN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. Typical Application Circuit (ISHA Mode)
POWER SUPPLY DECOUPLING
DACs
SYSTEM BUS
Figure 15. AD5532B in an ATE System
Typical Application Circuit (DAC Mode)
The AD5532B can be used in many optical networking applications that require a large number of DACs to perform control and measurement functions. In the example shown in Figure 16, the outputs of the AD5532B are amplified and used to control actuators that determine the position of MEMS mirrors in an optical switch. The exact position of each mirror is measured using sensors. The sensor readings are muxed using four dual 4-channel matrix switches (ADG739) and fed back to an 8-channel 14-bit ADC (AD7856). The control loop is driven by an ADSP-2191M, a 16-bit fixedpoint DSP with three SPORT interfaces and two SPI ports. The DSP uses some of these serial ports to write data to the DAC, control the multiplexer, and read back data from the ADC.
1
AD5532B
32
MEMS MIRROR ARRAY
1 32
S E N S O R
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5532B is mounted should be designed so that the analog and digital sections are separated, and confined to certain areas of the board. If the AD5532B is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. For supplies with multiple pins (VSS, VDD, AVCC), it is recommended to tie those pins together. The AD5532B should have ample supply bypassing of 10 F in parallel with 0.1 F on each supply located as close to the package as possible, ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching.
1
ADG739
4 8
AD7856
AD8544
2
ADSP-2191M
Figure 16. Typical Optical Control and Measurement Application Circuit
REV. A
-15-
09/19/02 2:30 PM_GS
AD5532B
The power supply lines of the AD5532B should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the DIN and SCLK lines will help reduce crosstalk between them (not required on a multilayer board as there will be a separate ground plane, but separating the lines will help). Note that it is essential to minimize noise on VIN and REFIN lines. Particularly for optimum ISHA performance, the VIN line must be kept noise-free. Depending on the noise performance of the board, a noise filtering capacitor may be required on the VIN line. If this capacitor is necessary, then for optimum throughput it may be necessary to buffer the source that is driving VIN. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a doublesided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. As is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of the package during the assembly process.
OUTLINE DIMENSIONS 74-Lead Chip Scale Ball Grid Array [CSPBGA] (BC-74)
Dimensions shown in millimeters
A1 CORNER INDEX AREA 12.00 BSC SQ
11 10 9 8 7 6 5 4 3 2 1
A1
TOP VIEW
1.00 BSC
BOT TOM VIEW
A B C D E F 10.00 BSC SQ G H J K L
1.00 BSC 1.70 MAX DETAIL A
DETAIL A
0.30 MIN 0.20 MAX COPLANARITY 0.70 SEATING 0.60 PLANE 0.50 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-192ABD-1
Revision History
Location 9/02--Data Sheet changed from REV. 0 to REV. A. Page
Term LFBGA updated to CSPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Changes to SERIAL INTERFACE table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Replaced Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Updated BC-74 package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 -16- REV. A
PRINTED IN U.S.A.
C02709-0-9/02(A)

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